To provide a communication processor and communication processing method capable of corresponding to multiple communication systems, while suppressing the increase of a circuit scale.
An arithmetic processing circuit resource 270 includes multiple programmable function units (FUs). An operation mode determination part 230 determines an operation mode which indicates a communication system application state. A permission processing time determination part 240 determines a permission processing time in accordance with the determined operation mode. A resource allocation part 250 distributes the multiple FUs according to the permission processing time, so as to allocate arithmetic resources by communication system indicated by the operation modes. An area control part 260 controls the allocated arithmetic resources. The arithmetic processing circuit resource 270 outputs data after the arithmetic processing at the timing when the arithmetic processing is completed.
KOBAYASHI SEIHO
MATSUOKA AKIHIKO
MARUYAMA TAKASHI
| JP2009171356A | 2009-07-30 | |||
| JP2002335186A | 2002-11-22 | |||
| JP2010522510A | 2010-07-01 |
| WO2009056504A1 | 2009-05-07 |