To provide a comparator which can prevent the operational speed from deteriorating due to the ON resistance or the parasitic capacitance of a transistor.
The comparator comprises a positive-phase variable resistance section 130, having a resistance variable that depends on the voltage of a positive-phase input signal and a negative-phase reference signal; a second variable resistance section 140, having a resistance variable depending on the voltage of a negative-phase input signal and a positive-phase reference signal; first and second switches for resetting the output potential of first and second inverters to the potential of a first or second power supply terminal, if the clock signal is at a first level; a first inverter 110 including a first FinFET for receiving the clock signal transiting between the first and second levels at one gate terminal and outputting a negative-phase output signal by making a positive-phase output signal inverted; and a second inverter 120 that includes a second FinFET of the same polarity as that of the first FinFET for receiving the clock signal at one gate terminal, and that outputs a positive-phase output signal by making a negative-phase output signal inverted.
KUROSE DAISUKE
UENO TAKESHI
ITAKURA TETSURO
| JPH09162408A | 1997-06-20 | |||
| JP2002118446A | 2002-04-19 | |||
| JP2005277352A | 2005-10-06 |
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto