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Title:
COMPLEMENTARY MOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH05129542
Kind Code:
A
Abstract:

PURPOSE: To highly integrate a complementary MOS semiconductor device by a method wherein the complementary MOS semiconductor device is formed in a direction perpendicular to the surface of a semiconductor substrate.

CONSTITUTION: An N-channel MOS and a P-channel MOS which are extended individually to a direction perpendicular to the surface of a P-type semiconductor substrate 11 and which are faced with each other are formed on the sidewall of an opening part 13. A common gate electrode 22 is formed inside the opening part 13. Thereby, the area occupied by a gate oxide film on the surface of the semiconductor substrate is reduced. In addition, since the gate electrode formed in the opening part can be used as a gate electrode which is common to a first-conductivity-type MOS and a second-conductivity-type MOS, the area occupied by the gate electrode on the surface of the semiconductor substrate is reduced. Consequently, a complementary MOS semiconductor device can highly be integrated.


Inventors:
TSUJI KAZUHIKO
Application Number:
JP28902291A
Publication Date:
May 25, 1993
Filing Date:
November 06, 1991
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/8238; H01L27/092; (IPC1-7): H01L27/092
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)