Title:
COMPRESSION CODE PACKING CIRCUIT
Document Type and Number:
Japanese Patent JPS6331372
Kind Code:
A
Abstract:
PURPOSE:To quickly perform n-bit packing by performing packing in accordance with the output of a shift circuit and that of the first storage circuit when the cumulative addition result of a packed compression code exceeds n-number of bits. CONSTITUTION:An n-bit end around bit shifter 1-d shifts the compression code, which is inputted from a register 1-b, by end around shift in accordance with the cumulative addition result of the compression code length inputted from a latch 1-e. If the cumulative addition value of the code length of the compression code exceeds n-number of bits, a data selector 1-g selects the output of a register 1-i and couples the code from the bit shifter 1-d following an effective code stored in the register 1-i. If the cumulative addition value does not exceed n-number of bits, the selector 1-g selects the output of a register 1-h and couples the code from the bit shifter 1-d following the effective code stored in the register 1-h. Thus, the variable length code of the output of an encoder 1-a is quickly subjected to the packing processing into n-bit data.
Inventors:
MURATA YUKIO
Application Number:
JP17498786A
Publication Date:
February 10, 1988
Filing Date:
July 25, 1986
Export Citation:
Assignee:
CANON KK
International Classes:
H04N1/41; G06F5/00; H03M7/30; H04N1/411; (IPC1-7): H03M7/30; H04N1/411
Attorney, Agent or Firm:
Marushima Giichi
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