PURPOSE: To perform transfer between main memory and a resist and an arithmetic operation between the resists by a CPU even while a DMA controller performs DMA transfer.

CONSTITUTION: When the DMA transfer is performed, the CPU 2 delivers a transfer address to the DMA controller 8 via a shared bus 1 first. The transfer address designates the address of buffer memory 5, not that of the main memory 4. Thence, the DMA controller 8, etc., is started up by delivering a series of commands from the CPU 2 to the DMA controller 8, and switching so as to connect a DMA pass selector 7 to a memory pass selector 6 is performed. The DMA controller 8 transfers received data as increasing or decreasing the number of transfer addresses. The memory pass selector 6 decodes part of received transfer addresses, and write is performed by automatically selecting the buffer memory 5.