To prepare a shared system cache in a system controller and to make the directly referable to the shared data of the shared system cache without referring to a main storage.

The processors IP0 1-IP3 4 have the caches CS0 11b-CS3 14b and their address management tables TAG0 11a-TAG3 14a respectively. A system controller SC 5 has the copied tables FAA0 11c-FAA3 14c and a shared system cache SCS 17, and the entry of each FAA is provided with an SV bit to show the valid/invalid state of the data stored in the SCS 17. When an access request is inputted from a processor to a shared storage MS 6, the controller SC 5 generates a control signal from a V(valid) bit obtained by referring to every FAA and the SV bit and in response to the access request address, and then controls the V bits of the MS 6 and the SCS 17 and the SV bit according to the generated control signal.