To reduce processor malfunction due to unstable clock signals right after a clock supply start.

The computer system is provided with a constantly operated processor, and an auxiliary processor 100. When the auxiliary processor 100 is not activated, a system clock signal Ck1 from a clock driver 104 is blocked by an AND circuit 117, and it is not supplied to the auxiliary processor. In response to an auxiliary processor activation instruction from a service processor 101, supply of a clock signal Ck2 from the AND circuit 117 is started while asserting a reset signal Rs from a signal transmission mechanism 111 to the auxiliary processor 100, and after passage of a period equivalent to stabilization of the clock signal Ck2, the reset signal Rs to the auxiliary processor 100 is negated.