Title:
乗算のための計算ユニット、方法及びコンピュータプログラム
Document Type and Number:
Japanese Patent JP7247418
Kind Code:
B2
Abstract:
A processing unit for multiplying a first value by a first multiplicand, or for multiplying the first value by, in each instance, a second and third multiplicand. The processing unit receives the multiplicands in a logarithmic number format, so that the multiplicands are each present in the form of at least one exponent at a specifiable base. The processing unit includes a first register, in which either two exponents of the first multiplicand or the exponent of the second and the exponent of the third multiplicand are stored. A set configuration bit indicates whether either the two exponents of the first multiplicand or the exponent of the second and the exponent of the third multiplicand are stored in the first register. The processing unit includes at least two bitshift operators. A method and a computer program for multiplying the value by the multiplicand are also described.
Inventors:
Sebastian Vogel
Application Number:
JP2022507493A
Publication Date:
March 28, 2023
Filing Date:
July 14, 2020
Export Citation:
Assignee:
ROBERT BOSCH GMBH
International Classes:
G06F7/523; G06F17/10; G06G7/60
Other References:
VOGEL SEBASTIAN ET AL,Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration,Design, Automation And Test in Europe (DATE 2019),2019年03月25日,pages 1094-1099
VOGEL SEBASTIAN ET AL,Efficient Hardware Acceleration of CNNs using Logarithmic Data Representation with Arbitrary log-base,2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD),2018年11月05日,pages 1-8
SYED SHAKIB SARWAR ET AL,Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing,2016 Design, Automation & Test in Europe Conference & Exhibition,2016年02月27日,pages 145-150
VOGEL SEBASTIAN ET AL,Efficient Hardware Acceleration of CNNs using Logarithmic Data Representation with Arbitrary log-base,2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD),2018年11月05日,pages 1-8
SYED SHAKIB SARWAR ET AL,Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing,2016 Design, Automation & Test in Europe Conference & Exhibition,2016年02月27日,pages 145-150
Attorney, Agent or Firm:
Einzel Felix-Reinhard
Taku Morita
Junichi Maekawa
Hideo Nagashima
Ueshima class
Taku Morita
Junichi Maekawa
Hideo Nagashima
Ueshima class