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Patent Searching and Data


Title:
CONNECTION OF INTEGRATED CIRCUIT ELEMENT
Document Type and Number:
Japanese Patent JPS6482646
Kind Code:
A
Abstract:

PURPOSE: To easily connect the electrodes of an integrated circuit element to opponent conductors by forming by plating outer and inner lead bumps at both ends of a finger lead.

CONSTITUTION: A tape carrier 1 is formed by laminating in advance the patterns of finger leads 2 to be connected to the electrodes 5 of an IC chip 4 on both side polyimide films. Windows are opened on both side faces to expose both ends of the lead 2. The exposed both ends are Ni-plated as diffusion preventive layers 21, then Au-plated on the Ni films, one of which becomes outer lead bumps 91 and the other of which becomes inner lead bumps 92. The electrodes 5 of the chip 4 are superposed on the bumps 91, conductors 8 to be connected are positioned on the bumps 92, and simultaneously connected by applying heat and pressure thereto by a bonding tool.


Inventors:
YAMADA FUMIAKI
KOBAYASHI HIROAKI
Application Number:
JP24171687A
Publication Date:
March 28, 1989
Filing Date:
September 25, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/603; H01L21/60; (IPC1-7): H01L21/603
Attorney, Agent or Firm:
Sadaichi Igita