Title:
FAULT DETECTION FACTOR CALCULATING METHOD FOR TEST PATTERN AND DEVICE THEREOF
Document Type and Number:
Japanese Patent JP3184023
Kind Code:
B2
Abstract:
PURPOSE: To provide the fault detection factor calculating method for a test pattern and its device capable of calculating the fault detection factor on the bridging fault of the test pattern.
CONSTITUTION: Two nodes A1, B1 are selected in a net list, an exOR gate D inputted with signals from two selected nodes A1, B1 is virtually inserted into the net list, and the new net list is logically simulated, with the output signal from the exOR gate D used as a virtual external output terminal T. Whether '1' is outputted from the virtual external output terminal T for a sufficiently long period during this logical simulation or not is checked, this check is repeated for a combination of two other nodes, and the fault detection factor of the test pattern is calculated from the ratio between the number of all combinations and the number of detections of '1'.
Inventors:
Toshihiro Takahashi
Application Number:
JP24236293A
Publication Date:
July 09, 2001
Filing Date:
September 29, 1993
Export Citation:
Assignee:
株式会社リコー
International Classes:
G01R31/28; G06F11/22; G06F11/25; G01R31/3183; G06F17/50; (IPC1-7): G01R31/3183; G06F11/25; G06F17/50
Domestic Patent References:
| JP777562A | ||||
| JP755894A | ||||
| JP755887A | ||||
| JP6194418A | ||||
| JP5264676A | ||||
| JP58207719A | ||||
| JP5682467A |
Attorney, Agent or Firm:
Hiroshi Torii
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