PURPOSE: To speed up plotting by performing one reading action and plural plotting actions in one cycle of display timing and operating a memory element comprising a frame memory in a minimum cycle time.

CONSTITUTION: A display data control circuit 6, a plotting timing control circuit 7, a plotting data control circuit 8 are operated at the same timing, which is generated using the minimum cycle time of the memory element comprising the frame memory 3 as one cycle. Since a display data converting circuit 9 converts all data to be displayed during one horizontal scanning period into video signals to output said data to a display device 2, a data buffer 4 stores the display data in that term. The circuit 6 reads data necessary during one horizontal scanning period out of the memory 3 according to a request signal from the buffer 4, and the data is temporarily stored in the buffer 4. Afterward, the display data is sequentially outputted to the circuit 9 at the timing generated by the display timing control circuit 5 during one horizontal scanning period.