PURPOSE: To reduce the deterioration of performance of a branch instruction due to the failure of branch prediction by preventing the invalidation of an entry corresponding to a branch predicting buffer in a branch failure mode with a branch instruction for loop control.

CONSTITUTION: An instruction extracting address set at a virtual address register 1 is sent to the extracting instruction address registers 9 and 10 which hold the address range of the extracted instruction. When the contents already set to the branch predicting buffers 4 and 5 go to wrong owing to the fact that a branch instruction does not exist any more due to the rewriting of instruction, that the branching destination address is changed and that the success of branch is changed to the failure, etc., the effective display bits in a branching predicting buffer K3 are reset. Then, the corresponding entry is invalidated. However the corresponding entry is never reset even though the branch fails with a control branch instruction of a DO loop used by an FORTRAN program, etc. since the same loop is used many times.