PURPOSE: To accelerate processing speed by performing block transfer by supplying a column address to main storage while counting up at every transfer of data after supplying a row address.

CONSTITUTION: Such control that the outputs of signals *RAS, *CAS, *WE, and *OE can be issued with prescribed timing are performed separately on plural sets of main storage 12, 13. In other words, when the block transfer is performed, after asserting *RAS once to the plural sets of main storage 12, 13, *CAS is controlled at every system cycle hereafter. Therefore, it is possible to realize one time of data transfer with one system cycle, which enables fast block transfer of six times compared with the conventional case. In such a manner, the processing speed of a device can be remarkably accelerated.