PURPOSE: To reduce labor and time required for fault analysis by adding an address coincidence detecting circuit for detecting coincidence between a storage starting resist setting up an optional instruction and an executing program to the title system.

CONSTITUTION: In order to execute a program instruction A, a fetch address signal 12 for an instruction A is inputted from a control unit 5 to an address coincidence detecting circuit 16. At that time, the address signal 12 coincides with a signal outputted from a storage start address register 15. An address coincidence signal 17 is inputted from the detecting circuit 16 to the control unit 5 and the unit 5 sends a storage stop signal 81 to a state history storage device 6. At the time of generating a fault, an operator stops an information processor by a device stop signal 91 through a service processor 7 and reads out state history information 11 precedently stored in the storage device 6 to utilize the information 11 for the analysis of a fault.