Title:
CONTROLLER OF EXTENDED MEMORY
Document Type and Number:
Japanese Patent JPS55131865
Kind Code:
A
Abstract:
PURPOSE: To reduce greatly a load on software by selectively controlling all addresses by generating a chip selective signal and then by selecting fixed areas of extended RAM by this signal.
CONSTITUTION: Central processing unit CPU1 is equipped with basic RAM4 including a user area and system area. Then, the user area of RAM4 is assigned. By combining an address selective signal with a signal assigning a fixed area in an extended memory, address circuit 8 generates a chip selective signal, so that a fixed area in extended RAM7 can be selected by the chip selective signal. Consequently, the entire extended RAM7 can effectively be used, all addresses can continuously be controlled, and a load on software can greatly be reduced.
Inventors:
MAEKAWA TOSHIYUKI
INOSAKI TOORU
YOSHIDA YUKIHIRO
INOSAKI TOORU
YOSHIDA YUKIHIRO
Application Number:
JP3921979A
Publication Date:
October 14, 1980
Filing Date:
March 30, 1979
Export Citation:
Assignee:
SHARP KK
International Classes:
G06F9/34; G06F9/32; G06F12/06; G06F13/00; (IPC1-7): G06F9/32; G06F13/00