PURPOSE: To reduce buffer memory capacity and to reduce variation in tape running speed extremely, by controlling a tape speed on the basis of the difference between the write and read addresses of the buffer memory of a time axis compensating circuit.
CONSTITUTION: As a tape speed increases more and more, the frequency of a reproduced digital signal increases more and the frequency of a write clock signal 13 synchronizing with it also increases to allow a write address counter 12 to count faster than a read address counter 14, so the difference between the write address and read address becomes greater than an initial value 50. For example, a subtracting circuit 18 outputs 52. Then, the frequency of the output signal 22 of a frequency dividing circuit 19 is N/52, which is lower than N/50 during constant-speed running operation. Consequently, a capstan motor driving circuit 21 operates to decrease the tape speed to a specific speed.
MATSUSHIMA KOUJI
KATOU MISAO
SUENAGA HARUO
