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Title:
CONTROLLER
Document Type and Number:
Japanese Patent JPS59139783
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of lines by disabling a level discriminating circuit just for a time longer than the changing delay time of a signal sent from a slave device owing to the stray capacity generated between lines by using a disabling circuit which is provided in response to the level disabling circuit.

CONSTITUTION: A disabling circuit 70 contains a comparator M6 and a buffer 71 which receives the signal from a resistance R15. The buffer 71 has a high input impedance and sets an output terminal 72 at a high and low level when the input of the buffer 71 is set at a high and low level respectively. The terminal 72 charges quickly a capacitor C via a diode D14, etc. connected forward to a resistance R32. The output voltage of the capacitor C is inverted by an inverter 74. Then the inverter 74 sets its output at a low potential and delivers a signal of a high potential when the level of the input terminal is higher and lower than the discriminating level respectively.


Inventors:
HARA YUUJI
Application Number:
JP1358483A
Publication Date:
August 10, 1984
Filing Date:
January 28, 1983
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H05B37/02; G08C19/02; H04Q9/06; (IPC1-7): H04Q9/06; H05B37/02
Attorney, Agent or Firm:
Nishikyo Keiichiro



 
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