PURPOSE: To equivalently realize a high speed D/A conversion with a low speed D/A converter by latching each sample value of a digital data while being distributed into plural latch circuits and using the D/A converter provided to the output of each latch circuit so as to apply D/A conversion to the latched data.
CONSTITUTION: Digital inputs D1, D2... are latched in latch circuits 20, 22 alternately by a latch signal CK at every two sampling periods. The latched data is D/A-converted by D/A converters 24, 26 as it is and inputted to switches 28, 30. Although the output of the D/A converters 24, 26 is unstable for the settling time, since each input data is latched for 2-sampling period, the switches 28, 30 are turned on for one stable sampling period after the settling time by using signals Q, Q to extract the conversion output. A conversion output without noise after the elapse of the settling time is obtained at the output of an amplifier 32. No capacitor is required for the output of the D/A converter and an accurate output is extracted.
JPS57140026A | 1982-08-30 | |||
JPS59223020A | 1984-12-14 | |||
JPS6045534B2 | 1985-10-09 |