Title:
A/D CONVERTER CIRCUIT
Document Type and Number:
Japanese Patent JP3221133
Kind Code:
B2
Abstract:
PURPOSE: To realize an A/D converter circuit in which high speed conversion processing is attained, the chip area is decreased and the power consumption is reduced.
CONSTITUTION: A low-order encoder 140 dividing Low-order codes into two groups to obtain a conversion code in response to each group generates selection signals SEL1, SEL2 to select L and R mode data outputted from a high-order encoder 120 and a selection gate 150 selectively outputs the L or R mode data based on the selection signals SEL1, SEL2.
Inventors:
Kunihiko Izuhara
Application Number:
JP3575893A
Publication Date:
October 22, 2001
Filing Date:
February 24, 1993
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03M1/14; H03M1/36; (IPC1-7): H03M1/14; H03M1/36
Domestic Patent References:
| JP1190029A | ||||
| JP2123829A | ||||
| JP2125530A | ||||
| JP2126725A | ||||
| JP2128524A | ||||
| JP2141028A | ||||
| JP2132920A | ||||
| JP2137420A | ||||
| JP2202224A | ||||
| JP4196923A | ||||
| JP63299615A | ||||
| JP277931U |
Attorney, Agent or Firm:
Takahisa Sato