PURPOSE: To make the applied range free, by making a convolution processing circuit unit and suitably combining a plurality of units according to the spread of transfer functions.

CONSTITUTION: A plurality of processors P1∼Pn are in series connection with multistage. Each processor consists of a shift register section which consists of shift registers SR11∼SR33 and line shift registers LSR1, LSR2 for one video element's share picking up a digital video information in, e.g., 3×3 constitution specific video element area, memory ROM stored with correcton function according to the correcting rnage of 3×3 constitution, and operation device OPC performing the product sum operation for the convolution according to the data relating to the density level of each video element picked up at the shift registers SR11∼SR13 and to the memory content. The application with a broad range can be made by providing the processors in series by the number required for the spread of a transfer function.