To reduce the quantity of acquired coordinate data and to suppress the power consumption of a coordinate position input device by reducing and increasing the sampling interval with large and small variation degrees of the coordinate data against the time respectively.

A comparator 9 compares the most significant bit 113 (7) of the digital coordinate data 113 (7:0) on an AD converter 5 with the most significant bit 114 (7) of the data coordinate data 114 (7:0) given from a D flip-flop 11. If both bits are not coincident with each other, level '1' is outputted from an EXOR gate 31 and an OR is secured at an OR gate 30 between the 1-level output of the gate 31 and a signal 118 sent from a control circuit 6. Then a reset signal 102 is outputted and then inputted to a register 7 and a counter 8 respectively. A signal 115 of the comparator 9 is inputted to an AND gate 15 and a D flip-flop 12, and an OR is secured between the signal 115 and an output level corresponding to a chip signal 105 sent from the gate 15. Then a shift direction designation signal 108 is outputted.