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Title:
CORRECTING CIRCUIT FOR RECORDING TIMING
Document Type and Number:
Japanese Patent JPS61258309
Kind Code:
A
Abstract:

PURPOSE: To prevent such malfunctions as the data errors, the malfunctions of a VFO circuit, the misdetection of an address mark in a search mode, etc. which are caused when the number of magnetization inverting signals is decreased or brought to naught, by producing said signals at all times.

CONSTITUTION: A magnetization inversion security circuit 10 consists of an inverter circuit 35, a delay circuit 34, an FF 40 and an AND circuit 42. This circuit 10 always secures the production of the magnetization inverting signals with the timing equivalent to the slowest timing of a recording timing correction circuit 3. Thus the reproduction of data is possible even in case no magnetization inverting signal is delivered owing to a trouble of the circuit 3. This eliminates such malfunctions as the reading errors, the deterioration of performance of a VFO circuit, the misrecognition of an address mark in a searching mode, etc.


Inventors:
HORIE TSUNEO
TAKEUCHI TAKIICHI
ICHIBA TADAYUKI
Application Number:
JP10086985A
Publication Date:
November 15, 1986
Filing Date:
May 13, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11B5/09; (IPC1-7): G11B5/09
Attorney, Agent or Firm:
Masatoshi Isomura



 
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