PURPOSE: To attain the reduction of a chip area by adding a means to a coupling element to compare the present degree of coupling with the intensity of a 1st signal together with a means which writes a new degree of coupling when the coincidence is secured with the comparing means.

CONSTITUTION: A staircase wave generating circuit 5 produces a staircase wave S of the n-th stage at an n-th cycle of a clock CL. At the same time, a write voltage generating circuit 4 produces the new write voltage P1 corresponding to the potential of the wave S. Then a sense amplifier consisting of transistors 15, 16, 23 and 24 compares the potential of a nodal point N2 of a coupling element W11 with the wave S which successively increases. When it is desired to change a degree of coupling corresponding to the potential VP of a capacitor 26 to that corresponding to f(VP), the potential of a signal P1 of the wave S of the m-th stage is set at (f(mΔV) + VTH) when the step of the wave S is set at ΔV. Thus a new degree of coupling is written into a capacitor 25. As a result, the area of the coupling element is reduced together with reduction of a chip area compared with a case where a counter, etc., are used.