制限付きゲートレベルレイアウトアーキテクチャにおける交差結合トランジスタレイアウト

Japanese Patent JP5628050

B2

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

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ベッカー スコット ティー

JP2010550861A

November 19, 2014

March 12, 2009

Click for automatic bibliography generation  

テラ イノヴェイションズ インコーポレイテッド

H01L21/8244; H01L21/82; H01L21/822; H01L27/04; H01L27/11

辻居 Koichi
Sadao Kumakura
Fumiaki Otsuka
Takayoshi Nishijima
Hiroyuki Suda
Hiroshi Uesugi
Yoshinobu Iwasaki

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