PURPOSE: To remove time loss when measuring is performed without causing disturbance, by providing reset terminals in a frequency dividing circuit, which divides the output of an oscillating circuit having a crystal temperature sensor and in a delay circuit using an up counter.

CONSTITUTION: An output signal S1 of a reference clock generating circuit 1 is inputted to an AND gate 2. An output signal S2 of an oscillating circuit 4 of a crystal temperature sensor 3 is divided by a frequency dividing circuit 5 and the result is inverted by an inverter gate 9 and inputted to the AND gate 2. The frequency divided signal of the signal S2 is a 0 directly after the circuit 5 is reset. Therefore, the reference clock signal S1 is inputted to a counter circuit 10. Thus the frequency dividing period of the signal S2 is measured. When the final stage of the circuit 5 rises up, the input of the signal S1 is stopped. At the same time, a delay circuit 8 starts the counting of the delay time. During this time, a microcomputer 11 processes the measured data of the circuit 10. When this is finished, the circuit 10 is reset. The circuit 8 resets the circuit 5 after the counting.