Title:
データ変換回路、および表示装置
Document Type and Number:
Japanese Patent JP7075752
Kind Code:
B2
Abstract:
Image processing in accordance with the shape of a display device is performed at high speed with low power consumption, without the use of a large frame memory or a high-throughput GPU. Used is a data conversion circuit including: a latch circuit that takes in data from input data in synchronization with a writing clock signal and stores the data as writing data; a memory circuit that stores the writing data and outputs the writing data to an external circuit as readout data in synchronization with a readout clock signal; and a clock selection control circuit. The writing clock signal is one of a plurality of clock signals with different frequencies and is output in accordance with control by the clock selection control circuit.
Inventors:
Yuki Okamoto
Seiichi Yoneda
Seiichi Yoneda
Application Number:
JP2017236649A
Publication Date:
May 26, 2022
Filing Date:
December 11, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09G3/20; G09G3/3208; H04L7/00
Domestic Patent References:
| JP11327499A | ||||
| JP9214864A |
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