PURPOSE: To speed up the merge processing due to an exclusive data merge instruction by controlling keys which control the size of key of data with on/off of an effective display bit and an identification display bit stored in a control bit register.

CONSTITUTION: A head key address, key length, interval with a key of the next record and record number of data A, B are set to a key address generating section 26, a high-order one word of the head key is read in registers 20, 21 from each data, compared with a comparator 22 and two signals representing the quantity of both partial keys are outputted. A control bit setting section 23 references a comparator output, an effective display bit of control bit registers 24, 25 set by the preceding processing and identification display bit and generates a revised value of each control bit, stores it in the control bit registers 25, 25, a key address generation section 26 references the output of the control bit setting section 23 and advances step by step the key address data A or B and reads the result to the register 20 or 21.