PURPOSE: To perform the fast processing of a CPU by providing a data buffer and a circuit to control the data buffer and an external memory on the inside of a microcomputer, and performing a processing independently from the CPU when an external data write instruction is received from the CPU.

CONSTITUTION: When a SYSCLK signal goes to a 'High' level, the transfer processing of data is performed on a data bus 4b. At such a case, write on a built-in memory 2 is performed when an INWRIT signal 1b is set at the 'High' level, and the write on an external memory 3 is performed when an OUTWRIT signal 2b is set at the 'High' level. Even when the write on the external memory 3 is performed, the write on the data buffer 5 is performed similarly at the same timing to perform the write on the built-in memory 2 with a control part 4. The CPU 1 executes following instructions after performing the instruction processing. During that time, a WRT signal 6b is outputted from the control part 4, and an external data bus 5b is outputted from the data buffer 5 while synchronizing with the signal 6b.