To provide a phase comparator circuit that reduces the effects of an offsets and jitters and to provide a data PLL circuit, that is mounted with the phase comparator circuit.

This data PLL circuit is provided with a DLL circuit 21, that receives input data PLDT and outputs a delayed signal PLDTD with a delay, in response to an oscillated frequency of a voltage-controlled oscillator (not shown) with respect to the input data PLDT, a D flip-flop F 21 that outputs the delayed signal PLDTL by latching the input data PLCK, on the basis of an oscillated clock PLCK outputted from the voltage controlled oscillator, and a phase comparator 22 that compares the phase of the delayed signal PLDTD with the phase of the delayed signal PLDTL.