Title:
ニューラルネットワークを利用したデータ処理装置、電子部品、および電子機器
Document Type and Number:
Japanese Patent JP7073090
Kind Code:
B2
Abstract:
To provide a data processing device using a neural network that can suppress increase in the occupied area of a chip. A product-sum operation circuit is formed using a transistor including an oxide semiconductor having an extremely small off-state current. Signals are input to and output from the product-sum operation circuits included in a plurality of hidden layers through comparators. The outputs of the comparators are used as digital signals to be input signals for the next-stage hidden layer. The combination of a digital circuit and an analog circuit can eliminate the need for an analog-to-digital converter or a digital-to-analog converter which occupies a large area of a chip.
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Inventors:
Takayuki Ikeda
Application Number:
JP2017244583A
Publication Date:
May 23, 2022
Filing Date:
December 21, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/60; G06N3/063
Domestic Patent References:
| JP6187472A | ||||
| JP2000057244A | ||||
| JP2016219011A | ||||
| JP2016218513A | ||||
| JP2741793B2 | ||||
| JP2003263624A |
Foreign References:
| US9430735 | ||||
| WO1993008538A1 | ||||
| US20040084727 | ||||
| US6377194 |
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