Title:
DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD
Document Type and Number:
Japanese Patent JP3049003
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To transfer data between a power PC processor and an input/output device even when respective little endian byte orders are different by providing the power PC processor, the input/output device and a memory controller for transmitting the data between both of them.
SOLUTION: This system is provided with a CPU 710 for using a power PC little endian byte order, an I/O adapter 718 for using a true little endian byte order and a memory controller sub system 501 for communicating the data between the CPU 710 and the I/O adapter 718. The memory controller sub system 501 converts the data transferred from the I/O adapter 718 to the CPU 710 or a memory 714 from the true one to the power PC little endian byte order. The data transferred from the CPU 710 or the memory 114 to the I/O adapter 718 are converted from the power PC one to the true little endian byte order.
Inventors:
John Michael Kaiser
Warren Edward Marl
Robert Dominique Mirabella
Devot Wine Victor
Warren Edward Marl
Robert Dominique Mirabella
Devot Wine Victor
Application Number:
JP8892398A
Publication Date:
June 05, 2000
Filing Date:
April 01, 1998
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F12/04; G06F5/00; G06F7/76; G06F13/40; (IPC1-7): G06F12/04; G06F5/00
Domestic Patent References:
| JP8305628A | ||||
| JP4163656A |
Other References:
奥井 和紀 監訳「ＰｏｗｅｒＰＣアーキテクチャ」（１９９５−１２−２０）、株式会社オーム社ｐ２０７−２２０
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)
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