Title:
DATA PROCESSOR EQUIPPED WITH DEVELOPMENT SUPPORT FEATURE
Document Type and Number:
Japanese Patent JPH01161448
Kind Code:
A
Abstract:
PURPOSE: To simplify constitution by providing a first means for executing instructions, a second means for utilizing system resources corresponding to the execution of the first means of first plural instructions and a third means for accessing the system resources corresponding to the execution of the first means of second plural instructions. CONSTITUTION: An alternate operating mode for propagating the instruction by an externally controlled bus is provided. Since a sequence 53 controls the progress of the instruction through an IR pipe 51 stage and supplies output signals IPIPE and IFETCH, an external development system continuously monitors the contents of the IR pipe 51. The sequence 53 claims the IPIPE tar one clock cycle when the first stage of the pipe is advanced to a second stage and claims the TPTPE for two clock cycles when the first stage is advanced to the second stage and the second stage is advanced to a third stage. The IFETCH is claimed for one clock cycle when a present bus cycle takes out the instruction and is claimed for two clock cycles when the IR pipe 51 is cleared or made to so-called flow out. In such a manner, the constitution is simplified.
Inventors:
JIYON JIEI BAGURIKA
JIEI EE HAATOBIGUZEN
RANDO ERU GUREI
JIEI EE HAATOBIGUZEN
RANDO ERU GUREI
Application Number:
JP27434288A
Publication Date:
June 26, 1989
Filing Date:
October 29, 1988
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
G06F11/28; G06F9/30; G06F9/318; G06F9/455; G06F11/36; G06F15/78; G06F11/267; (IPC1-7): G06F9/44; G06F11/28; G06F15/06
Domestic Patent References:
| JPS59146352A | 1984-08-22 | |||
| JPS62197855A | 1987-09-01 |
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)