To prevent the occupancy ratio of an execution instruction in a memory for instruction storage from falling by providing a memory which stores an instruction code string that represents a specific instruction code string in a compressed form and its compressed configuration indication information and extending it in terms of hardware at the time of execution.
Instruction storage memory 1 stores an instruction code string that is represented in a compressed form at least about a specific instruction code string and compressed configuration indication information that shows a compressed configuration about the instruction code string. An instruction code restoring circuit 2 restores an instruction code string read from the memory 1 to an incompressed state based on the compressed configuration indication information that is added to the instruction code string. Thereby, it is possible to eliminate NOP(No Operation) instructions that cause to increase a load module capacity in a VLIW processor from a load module and to compress the load module.
YASUSATO AKIRA
JPS5428087A | 1979-03-02 |