To perform efficient memory access without a failure even in use of a relatively low-speed memory.

The data processor comprises an arbitration means for arbitrating bus use requests outputted from a plurality of bus masters connected to a bus based on priority orders set in the plurality of bus masters; an arbitration control means for controlling, according to a bus master permitted to use the bus just before, the arbitration means to perform the arbitration after a predetermined time; and an arbitration timing change means for changing, according to the bus master permitted to use the bus just before and the priority orders, the timing of arbitration.

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