Title:
DATA PROCESSOR
Document Type and Number:
Japanese Patent JP3441996
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accelerate the operation of a data processor by providing physical constitution for considering the delay amount of address signals, reaching a cache memory and obtaining cache memory operation timing control signals provided with an optimum timing.
SOLUTION: This data processor is provided with an instruction address generation part 20 for generating address signals S22, an instruction cache operation clock generation part 10 for generating address synchronization clock signals S10 provided with a timing matched with the change timing of the address signals S22 and an instruction cache 30. By controlling the operation timing of the instruction cache 30 by using the address synchronization clock signals S10, timing design without waste at the time of performing cache memory access is made possible.
Inventors:
Hiroaki Yamamoto
Shinji Ozaki
Yoshito Saimichi
Shinji Ozaki
Yoshito Saimichi
Application Number:
JP8563999A
Publication Date:
September 02, 2003
Filing Date:
June 02, 1995
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F12/08; G06F12/00; (IPC1-7): G06F12/00; G06F12/08
Domestic Patent References:
| JP240741A | ||||
| JP6149655A |
Attorney, Agent or Firm:
Hiroshi Maeda (1 person outside)
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