To provide the data processor which can reduce program size without narrowing down the range of addresses that can be specified.

A special FP(frame pointer) register indirect address specification mode is provided which can shorten an instruction code, and the instruction code which uses this address specification mode has specific constitution. Namely, an operation code OP is set as its 1st byte, and the high-order two bits of the 2nd byte are set toindicating operation size SZ is set with following two bits and ano-sign integer is set as a value indicating displacement DISP withthe low-order four bits of the 2nd byte. The value in theinstruction code which indicates DISP is shifted by one bit to theleft through a shifter 76 and a sign bit '1' is added as the mostsignificant digit bit to obtain a negative 6-bit even number, whichis added to the value of the FP register 18 by an adder 20 to obtainan effective address.