Title:
データ読み出し回路
Document Type and Number:
Japanese Patent JP4379641
Kind Code:
B2
Abstract:
A data reading circuit for a semiconductor memory device is provided that reduces noise effects by stably operating a latch sense amplifier during a high speed operation. The data reading circuit produces a stable output voltage. The data reading circuit includes a sense amplifier controller that generates a first pulse signal having a time width for fully equalizing a sense amplifier. The sense amplifier generates the first pulse signal by delaying an address transition detection signal while a high level read signal is being outputted. The sense amplifier controller also combines the address transition detection signal and the first pulse signal to output a second pulse signal. A first current mode dual latch sense amplifier senses a data signal from a memory cell in accordance with the second pulse signal from the sense amplifier controller and transfers the sensed data in accordance with the first pulse signal. The data reading circuit produces a stable output voltage without generating an increased width address transition detection signal.
Inventors:
Kyun Saen Kim
Application Number:
JP29799098A
Publication Date:
December 09, 2009
Filing Date:
October 20, 1998
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/41; G11C11/417; G11C7/06
Domestic Patent References:
| JP7085675A | ||||
| JP8096583A | ||||
| JP62140292A |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Kimio Matsumoto
Kakehi Yuro
Kimio Matsumoto