PURPOSE: To fast and correctly receive the data blocks having the lengths that exceed the upper limit transfer value settable to a direct memory address DMA controller, by inhibiting the output operations of an FIFO buffer as well as the input operations of a serial/parallel conversion means for a period during which a restart is applied after the end of the DMA transfer.

CONSTITUTION: The data received for a resetting period of the DMA transfer conditions set to a DMA controller 14 are held by a FIFO buffer 11. Under such conditions, the output of the buffer 11 is inhibited and then restarted when a resetting action is through. Thus it is possible to receive correctly and at a high speed even such a variable length data block having its length exceeding the upper limit value of the count number (transfer length) which is settable to the controller 14.