PURPOSE: To quickly convert the speed with a simple constitution without using an asynchronous memory by converting serial data of a low speed to parallel data by a serial-parallel converter and successively delaying these data by a time T×n and synthesizing them.

CONSTITUTION: The low speed 64kbps serial data D'0 to D'7 inputted to an input terminal (b) of a serial-parallel converter A are converted to parallel data D"0 to D"7 by a 64kHz clock signal inputted to an input terminal (a) and the converter A. They are sampled at the rise of a 512kHz clock signal by this clock signal of an input terminal C and DFFs B1 to B8 and are converted to sampling data D"0 to D"7. Data D'''0 to D'''7 are inputted to an OR gate D and are multiplexed after being delayed by the time T×n, and the result is outputted from an output terminal (d) of the gate D. Thus, 512kbps serial data D1 to D7 of high speed can be outputted from the terminal (d), and the speed is quickly converted with the simple constitution without using an asynchronous memory, and a device is made inexpensive and easily practical and is miniaturized.