PURPOSE: To transfer serial data at double speed by providing a set of latch means fetching data synchronously with rising/falling of a clock pulse to an input/output section at the transmission side and the reception side of the data.

CONSTITUTION: An output section of an LSI10 at the transmission side is provided with a set of latch stages 11a, 11b latching respectively two kinds of serial data D, d and a multiplexer 13 outputting selectively latched data to an output terminal 12. The latch means 11a, 11b latch the data (d) synchronously with the rising/falling of a clock pulse CLK. An input section of an LSI20 at the reception side is provided with delay inverters 26a, 26b, a set of latch means 21a, 21b fetching a signal at a data input terminal 22 with a signal 32 and a delay means 27 of latch data of the latch means 21a. An output of the latch means 11a is fetched to the latch means 21a and an output of the latch means 11b is fetched to the latch 21b one after another.