PURPOSE: To always output a correct bit train by arranging the bit train to be inputted to an error correction decoder, so as not to execute error correction decoding, and detecting the state of disabling the error correction for the error correction decoder.
CONSTITUTION: For bit trains D61 and D62 to be inputted to a viterbi decoder 71, the train orders of the correct bit trains D61 and D62 are inverted and further, the respective bits of one train are inverted. Therefore, the viterbi decoder 71 disables error correction decoding and frequently generates error. Even in a viterbi decoder 72, the similar thing occurs as well. Since the viterbi decoder generally monitors a bit error rate and outputs an alarm signal when the bit error rate is degraded over a threshold value, a reference carrier phase is forcedly changed at 90° by controlling the reference carrier reproducing circuit of a demodulator 50 with this alarm signal. Thus, the correct bit train is always obtained at a reception terminal.
KATO SHUZO
KUBOTA SHUJI
NIPPON TELEGRAPH & TELEPHONE