To exactly set a pedestal level after A/D conversion with a simple circuit configuration and to generate a clock signal in the fixed phase relation with a reference frequency signal.

A burst signal converted to digital by an A/D converter 22 is sampled in double subcarrier cycle (2Fc) at a 2nd sample circuit 30. At a comparator 36, sample data (SC) from the 2nd sample circuit 30 are compared with reference pedestal data (REF) from a pedestal data generating circuit 34. Only during a burst period when there is phase difference between both the data, a high-level or low-level signal is outputted from the comparator 36 to a clamp circuit 20. In accordance with this high-level or low-level signal, the capacitor of the clamp circuit 20 is charged or discharged, so that the clamp level of the clamp circuit 20 can be changed (fixed).