Title:
DECIDING CIRCUIT FOR INTERLOCK CONDITION
Document Type and Number:
Japanese Patent JPS6314201
Kind Code:
A
Abstract:
PURPOSE:To reduce the load on a CPU and to increase the processing speed of a system by storing interlock conditions in a memory and comparing memory contents corresponding to an output code from a CPU with the state of a position detector, bit by bit. CONSTITUTION:A timing signal generating circuit 16 when receiving an actuator code 15 from the CPU 14 outputs a head address corresponding to the code to input 1st-8th interlock master data 6 and interlock data 7 to shift registers 9 and 10 and also input 1st-128th pieces of position detection information 8 to a shift register 11 at the same time. Then, shift pulses 23 are outputted to the respective registers, whose contents are shifted. The pulses 23 are counted by a counter 19. Then when an interlock master data sequence 24, an interlock data sequence 25, and a position detection information sequence 26 are established, a condition decision result 31 is latched by a latch circuit 21. Then, a condition decision is made and when the result is true, a 9th and succeeding data are processed repeatedly; and the number of times of shifting and condition decision result are reported to the CPU 1 at the end of the processing.
Inventors:
YANO KIYOSHI
Application Number:
JP15603086A
Publication Date:
January 21, 1988
Filing Date:
July 04, 1986
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G05B9/02; B25J13/00; (IPC1-7): B25J13/00; G05B9/02
Attorney, Agent or Firm:
Katsuo Ogawa