Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
DECIMAL COUNTER
Document Type and Number:
Japanese Patent JPS5458343
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of pins of IC and its size, by making unnecessary the reset terminal, through the addition of the circuit releasing the agglutination caused at the initial stage of the decimal counter operation in FF circuit.

CONSTITUTION: The decimal counter is constituted with four T type FF's (FF1 to FF4) and three gate circuits. At this time, to one input terminal of the circuit NOR 1, the circuit in which the inversion signal of the output Q3 of FF3 and the output Q4 of FF4 are fed as the logical product output with the circuit AND is added. If the both of the outputs Q3 and Q4 are (1), the output of the circuit AND is (0) and the signal is input of the cricuit NOR 1, changing FF2 and further FF3. Accordignly, even if the output Q3 is (1), the output Q2 makes it (0) and the cause to the agglination, the both outputs Q3 and Q4 are (1), can be avoided


Inventors:
FURUHATA MAKOTO
Application Number:
JP12452377A
Publication Date:
May 11, 1979
Filing Date:
October 19, 1977
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H03K23/58; H03K23/00; (IPC1-7): H03K23/24