DECODE CIRCUIT, DECODE METHOD AND TIMING PULSE GENERATING CIRCUIT

Title:

DECODE CIRCUIT, DECODE METHOD AND TIMING PULSE GENERATING CIRCUIT

Document Type and Number:

Japanese Patent JP3655812

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To overcome the problem such that a conventional decode circuit used for a timing pulse generating circuit or the like and consisting of a combination of logic gates such as AND and OR gates, has caused excess power consumption in the case of CMOS process devices due to an output change resulting from a delay time difference of signals given to the OR gates or the like, that is, hazard.
SOLUTION: The decode circuit of this invention is a decode circuit provided with at least one n-input logic gate (n is an integer of 3 or over) and one of n-sets of input signals is a clock signal. The clock signal is given to the n-input logic gate earlier than the other data signals in terms of time. The logic gate is an OR gate or a NAND gate. This decode circuit causes no hazard because the clock signal masks factors causing the hazard.

Inventors:

Hiroyuki Endo

Application Number:

JP2000221228A

Publication Date:

June 02, 2005

Filing Date:

July 21, 2000

Export Citation:

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Assignee:

NEC Communication Systems, Ltd.

International Classes:

G06F1/06; G06F1/12; H03K5/1252; (IPC1-7): H03K5/1252; G06F1/06

Domestic Patent References:

JP10228491A
JP63287164A
JP5128200A
JP9204365A

Attorney, Agent or Firm:

Masahiko Desk
Kawai Nobuaki
Yasuhisa Tanizawa

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