To enable a decoder to conduct decoding accurately based on a common STC between a processor and an image decode means while the decoding of a transport stream is conducted on the processor and the reproducing of the STC is stably conducted.
The capacity of a 2nd buffer means 24 is set to be the capacity that absorbs dispersion in an arrival time due to arbitration and can conduct the supply of a packet to a processor 13 stably. Furthermore, this decoder is provided with a master clock generating circuit as a time reference and an STC is handed in a form of a difference between a master clock and a PCR to conduct the reproducing of the STC. Furthermore, a PCR input to an STC reproducing means is delayed by a delay time when the packet reaches the processor 13.
| JPH08163563 | STILL PICTURE DATA COMPRESSION DEVICE |
| JP3211545 | PICTURE PROCESSOR |
| JPH06165148 | DYNAMIC PICTURE COMMUNICATE EQUIPMENT |
KOMENO JUNICHI
UENO TAKAFUMI
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