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Title:
DECODER
Document Type and Number:
Japanese Patent JPS5545239
Kind Code:
A
Abstract:

PURPOSE: To stabilize operations when input signals are stopped, by providing an FF, which is inverted at every clock when the logic of a control terminal indicating presence and absence of input delta modulation signals indicates an input signal absence state, and a delta modulation code decoder.

CONSTITUTION: When a delta modulation code is inputted to terminal 8 and control terminal 9 is high-potential, AND circuit 12 is opened, and circuit 11 is closed, and input signals are inputted to the D input of FF 15 through OR circuit 13, and FF 15 shapes the waveform of them and transfers them to decoder 5. When input signals are stopped, terminal 9 becomes low-potential, and circuit 11 is opened, and circuit 12 is closed, and the Q inversion output is inputted to the D terminal of FF 15, and 0 and 1 are alternately inputted to decoder 5 repeatedly as the output of FF 15 at every clock input of terminal 10. As a result, the output of decoder 5 does not reach a saturation point, and a click sound generated when input signals are stopped is eliminated, thus performing stable operations.


Inventors:
TSUBOKA HIDEKAZU
MAEHARA FUMIO
Application Number:
JP11834178A
Publication Date:
March 29, 1980
Filing Date:
September 25, 1978
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03M3/02; H04B14/06; (IPC1-7): H03K13/22; H04B12/04



 
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