Title:
ダミー充填パターンを用いる半導体回路におけるデカップリングキャパシタの形成方法および半導体構造
Document Type and Number:
Japanese Patent JP4532803
Kind Code:
B2
Abstract:
A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
Inventors:
Reese, Armin, M.
Shoe, louis
Hafner, Hennink
Lehmann, Gunter
Shoe, louis
Hafner, Hennink
Lehmann, Gunter
Application Number:
JP2001537776A
Publication Date:
August 25, 2010
Filing Date:
November 02, 2000
Export Citation:
Assignee:
Infineon Technologies North America Corporation
International Classes:
G06F17/50; H01L21/02; H01L21/82; H01L21/822; H01L21/8242; H01L27/04; H01L27/108
Domestic Patent References:
| JP11204766A | ||||
| JP10242283A | ||||
| JP10150148A | ||||
| JP2058365A | ||||
| JP10150163A | ||||
| JP3016260A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office