Title:
区分線形近似を用いる深層ニューラルネットワークアーキテクチャ
Document Type and Number:
Japanese Patent JP7405493
Kind Code:
B2
Abstract:
In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.
Inventors:
Kamresh Pirei
Gurpreet S. Kalsi
Amit Mishra
Gurpreet S. Kalsi
Amit Mishra
Application Number:
JP2019100574A
Publication Date:
December 26, 2023
Filing Date:
May 29, 2019
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06N3/04; G06F7/533; G06F9/302; G06F9/38; G06G7/60; G06N3/063
Foreign References:
| US20160380653 | ||||
| US20170011288 |
Other References:
Sheikh, Farhana, et al.,A 2.05 GVertices/s 151 mW lighting accelerator for 3D graphics vertex and pixel shading in 32 nm CMOS.,IEEE journal of solid-state circuits 48.1 (2012),米国,IEEE,2012年12月05日,128-139,[online],令和5年6月16日検索],インターネット
Attorney, Agent or Firm:
Patent Attorney Corporation RYUKA International Patent Office
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