To attain high-precision AD conversion by increasing a sampling frequency by four times by controlling the sampling operation and integral arithmetic of 1st and 2nd ΔΣ system AD converters with output digital signals selected alternately by sampling clocks.

For four-fold sampling, the two ΔΣ system AD converters are operated as blocks BK1 and BK2 in different timing of one clock and a multiplexer 3 makes alternate choices, clock by clock, to obtain a digital output Y1. The analog input is sampled at intervals of two clocks by alternating some sampling operation mode A and sampling operation B which is two clocks after it. Further, the difference between the analog input and digital output is integrated at intervals of two clocks and the multiplexer 3 selects the comparator 11 or 12 at intervals of two clocks to send digital outputs Y11 and Y12 as a block BK1 output.